This invention relates to a signal processor using a pipeline architecture to process signals, e.g., video signals.
Conventionally, pipeline architecture has been used to enhance the throughput of digital signal processors. In the pipeline processing, one process is broken into a number of stages so as to perform one stage at the same time that another stage is being performed.
C. Joanblanq et al reported a programmable digital video signal processor for HDTV (high-definition television) in their work entitled "A 54-MHz CMOS Programmable Video Signal Processor for HDTV Applications", IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, pp. 730-734, Jun. 1990. This report shows a technique in which a single chip accommodates multistage-pipelined multiply-add arithmetic circuits to perform filter operations. In accordance with this technique, the transfer function of the filter is determined by a coefficient programmed to each of these multiply-add arithmetic circuits. The transfer function can be changed by simultaneously updating all the programmed coefficients during a line blanking interval while the filter is stopped.
An example as a result of generalizing the structure of the above-described type of conventional signal processor is illustrated in FIG. 12. As shown in the figure, three different arithmetic units (AUs), each of which forms a respective stage, are connected in series. In other words, pipeline processing is performed by these AUs. 201, 202, and 203 are first, second, and third AUs. These AUs 201, 202, and 203 perform pipeline processing in synchronism with a clock signal 204. For example, AUs 201, 202, and 203 are broken into three substages, two substages, and three substages, respectively. 205 is a control circuit which delivers first, second, and third control signals to AUs 201, 202, and 203. The first control signal controls the operation of AU 201. The second control signal controls the operation of AU 202. The third control signal controls the operation of AU 203. 210 is an input unit which provides input data 209 to AU 201 for every clock cycle. In response, AU 201 performs a first arithmetical operation on the input data 209, thereafter providing a result of the first arithmetical operation to AU 202. In response, AU 202 performs a second arithmetical operation on the output of AU 201, thereafter providing a result of the second arithmetical operation to AU 203. In response, AU 203 performs a third arithmetical operation on the output of AU 202, thereafter providing a result of the third arithmetical operation. AU 201 executes either PROCESS A or X according to the first control signal 206. AU 202 executes either PROCESS B or Y according to the second control signal 207. AU 203 executes either PROCESS C or Z according to the third control signal 208.
FIG. 13 is a diagram of pipeline processing by this signal processor. With PROCESS A broken into OPERATIONS A(1), A(2), A(8), AU 201 performs pipeline processing. With PROCESS B broken into OPERATIONS B(1), B(2), AU 202 performs pipeline processing. With PROCESS C broken into OPERATIONS C(1), C(2), C(3), AU 208 performs pipeline processing. Each OPERATION is completed in a single clock cycle.
At cycle t1, DATA (n) is fed to AU 201. Then, DATA (n) is subjected sequentially to PROCESSES A-C. At cycle t8, the processing of DATA (n) is completed, and cycle t9 provides a result of the processing of DATA (n). At cycle t2, DATA (n+1) is fed to AU 201. Then, DATA (n+1) is subjected sequentially to PROCESSES A-C. At cycle t9, the processing of DATA (n+1) is completed, and cycle t10 provides a result of the processing of DATA (n+2). At cycle t3, DATA(n+2) is fed to AU 201. Then, DATA (n+2) is subjected sequentially to PROCESSES A-C. At cycle E10, the processing of DATA (n+2) is completed, and cycle t11 provides a result of tile processing of DATA (n+1). This pipeline processing enables each cycle t9-t11 to yield a result of the processing.
When performing process switching to PROCESSES X-Z from cycle t4 at which DATA (n+3) is fed to AU 201, control circuit 205 tries to simultaneously update all the control signals 206, 207, 208. However, at cycle t4, PROCESS A has not been completed yet with respect to DATA (n+1) and DATA (n+2). Additionally, at cycle t4, with regard to DATA (n), DATA (n+1), and DATA (n+2), neither PROCESS B nor PROCESS C has been completed yet. This incompletion is a bar to simultaneously updating all the control signals 206, 207, 208. Control circuit 205 therefore will have to wait for cycle t11 to come, to simultaneously update all the control signals 206, 207, 208. To sum up, PROCESSES X-Z for DATA (n+3), DATA (n+4) and DATA (n+5) to be fed to AU 201 after cycle t4 and subsequent clock cycles will not be performed until cycle t11 (see FIG. 13).
The above-described signal processor proposed by C. Joanblanq et al employs a structure capable of performing simultaneous process switching during the line blanking interval, so that no problems will be produced as long as such process switching is completed within a line blanking interval. However, it is impossible to perform process switching from a certain pixel in a horizontal line. For example, it is impossible to perform process switching of PROCESSES A-C to PROCESSES X-Z, to handle DATA (n+3) from cycle t4. Further, it is simply impossible to frequently make process switching for every pixel.
Generally speaking, the signal processor of FIG. 12 is designed in such a way as to simultaneously change all the operations of AUs 201, 202, 203. This produces several drawbacks. For example, distortion of the pipeline operations occurs at the time when process switching is made, and the throughput of the signal processor becomes poorer.